In general a CCD comprises a body of a semiconductor material, such as single crystalline silicon, having a channel region in and along a surface of the body. A layer of an insulating material, typically silicon dioxide, is on the surface of the body and over the channel region. A plurality of conductive gate electrodes, typically of doped polycrystalline silicon, are on the insulating layer and extend across the channel region. The gate electrodes are positioned along the entire length of the channel region.
In a two-phase CCD, the gate electrodes are arranged in two sets which alternate along the channel region. The gate electrodes of one set are connected to a first phase potential, and the gate electrodes of the other set are connected to a second phase potential. Such a two-phase CCD also typically includes in the body a barrier region under an edge of each of the gate electrodes and extending across the channel region. The barrier regions prevent the charge from moving backwards along the channel region.
The two sets of gate electrodes could be formed from a single layer of the conductive material by depositing the single layer and defining it by photolithography and etching to form the spaced gates electrodes along the channel region. However, using commercial type photolithographic and etching techniques and equipment, it is difficult to form the gate electrodes having very narrow submicron gaps therebetween with the gaps being uniform across the entire width of the gate electrodes. Since relatively wide and/or non-uniform gaps can form potential barriers and/or wells between the gate electrodes, they can interfere with the transfer of charge from one gate electrode to the next. Therefore, it has been the practice to form the gate electrodes from two separate levels (layers) of the conductive material.
For a two level system, a first layer of the conductive material is deposited and defined to form one set of the gate electrodes, the first set of gate electrodes are covered with a layer of an insulating material, typically silicon dioxide. A second layer of the conductive material is then deposited over the first set of gate electrodes and the gaps between the first set of gate electrodes. The second layer of the conductive material is then defined to form the second set of gate electrodes which are between the gate electrodes of the first set. Also, each of the gate electrodes of the second set overlaps the adjacent gate electrodes of the first set. Since the gate electrodes overlap each other, there are no gaps therebetween which can form undesirable potential barriers and/or wells. However, the two level gate electrode system is non-planar since portions of the second set of electrodes extend over the first set of electrodes. Also, there is provided undesirable capacitance between the two sets of gate electrodes where they overlap.
Heretofore, submicron-gap, planar gate CCD structures have been reported, but they have been primarily three or four-phase devices. A two-phase submicron gap CCD is described in an article by V. J. Kapoor, published in IEEE Electron Device Letters, Vol EDL-2, No. 4, page 92, April 1981. However, the structure described in this article suffers from formation of potential wells and/or barriers between the barrier and storage regions within each phase resulting in low transfer efficiency. This is because this device is not a true two-phase structure, but has separate electrodes for the individual barrier and storage regions within each phase. Therefore, it would be desirable to have a method of making a true two-phase CCD having a single level of the gate electrodes so as to be planar, and having submicron gaps between the gate electrodes.